| SETUP_TIME | (cycles-1) of ¡°prepare¡± phase by spi clock, this bits combined with spi_cs_setup bit. |
| HOLD_TIME | delay cycles of cs pin by spi clock, this bits combined with spi_cs_hold bit. |
| CK_OUT_LOW_MODE | modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_L bits. |
| CK_OUT_HIGH_MODE | modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_H bits. |
| MISO_DELAY_MODE | MISO signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle |
| MISO_DELAY_NUM | MISO signals are delayed by system clock cycles |
| MOSI_DELAY_MODE | MOSI signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle |
| MOSI_DELAY_NUM | MOSI signals are delayed by system clock cycles |
| CS_DELAY_MODE | spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle |
| CS_DELAY_NUM | spi_cs signal is delayed by system clock cycles |